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	A reference-less all-digital burst-mode CDR with embedded TDC
	Jiang, Mengyin ; Wang, Yuan ; Liu, Baoguang ; Liu, Yuequan ; Jia, Song ; Zhang, Xing
	2015
英文摘要	In this paper, a 1.25 Gpbs all-digital burst-mode clock and data recovery (BM-CDR) circuit with embedded time-to-digital converter (TDC) is presented. The proposed BM-CDR circuit uses an amendatory calculation method to achieve less quantization error. Current-starved inverters with control signals are used to realize fine-TDC to improve the resolution and reduce the power. This circuit is implemented in a 65nm CMOS process. Simulation results show that the clock jitter is reduced from 0.24 UI to 0.027 UI, about 88.75% under 16-bit consecutive identical digits. ? 2015 IEEE.; EI
语种	英语
出处	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
DOI标识	10.1109/ASICON.2015.7517132
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/449294]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Jiang, Mengyin,Wang, Yuan,Liu, Baoguang,et al. A reference-less all-digital burst-mode CDR with embedded TDC. 2015-01-01.

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