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	A 6bit 4GS/s current-steering digital-to-analog converter in 40nm CMOS with adjustable bias and DFT block
	Zhao, Long ; He, Ji ; Cheng, Yuhua
	2015
英文摘要	In this paper, a 6-bit high-speed digital-to-analog converter (DAC) is presented. This DAC is based on a segmented architecture and has an operating speed up to 4GS/s according to the post-layout simulation results. The output waveform of this DAC is realized in a non-return-to-zero (NRZ) way. The DAC core occupies an area of 0.09mm2 in a 40nm CMOS technology. A DfT block is introduced to relieve the speed requirement of high-speed I/O. The spurious free dynamic range (SFDR) up to 44.81dBc is achieved over Nyquist interval. The power consumption is 13mW at near Nyquist frequency. ? 2015 IEEE.; EI
语种	英语
出处	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
DOI标识	10.1109/ASICON.2015.7517104
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/449293]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhao, Long,He, Ji,Cheng, Yuhua. A 6bit 4GS/s current-steering digital-to-analog converter in 40nm CMOS with adjustable bias and DFT block. 2015-01-01.

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