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Algorithmic and architectural co-design for integer motion estimation of AVS
Sheng, Bin ; Gao, Wen ; Xie, Don
刊名ieee transactions on consumer electronics
2006
DOI10.1109/TCE.2006.1706512
英文摘要The video part of AVS has been finalized. In order to enhance coding performance, AVS video standard adopts some new features for motion estimation, such as variable block size search, multiple reference frames, and motion vector prediction. However, the better performance comes at the price of high computational complexity, data dependence and memory access requirement. These new features also make the hardware implementation more difficult, especially for real-time applications. In this paper, we firstly propose an integer motion estimation algorithm from hardware-oriented viewpoint. Experimental results show that the proposed algorithm has almost the same performance as the reference software of AVS in SDTV applications. Then the corresponding VLSI architecture is presented. The VLSI architecture has been described in Verilog HDL and synthesized using 0.18??m Artisan CMOS cells library. The circuit totally costs about 400K equivalent logic gates. At 108MHz working frequency, the circuit can meet the real-time requirement for SDTV (720 ?? 576, 25fps) applications, with the search area of 192 ?? 192. The co-design obtains better tradeoff between performance and gate-count. ? 2006 IEEE.; EI; 0; 3; 1092-1098; 52
语种英语
内容类型期刊论文
源URL[http://ir.pku.edu.cn/handle/20.500.11897/410163]  
专题信息科学技术学院
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GB/T 7714
Sheng, Bin,Gao, Wen,Xie, Don. Algorithmic and architectural co-design for integer motion estimation of AVS[J]. ieee transactions on consumer electronics,2006.
APA Sheng, Bin,Gao, Wen,&Xie, Don.(2006).Algorithmic and architectural co-design for integer motion estimation of AVS.ieee transactions on consumer electronics.
MLA Sheng, Bin,et al."Algorithmic and architectural co-design for integer motion estimation of AVS".ieee transactions on consumer electronics (2006).
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