H.264 VBSME SAD algorithm and architecture for hardware optimization

CORC > 北京大学 > 信息科学技术学院

	H.264 VBSME SAD algorithm and architecture for hardware optimization
	Peng, Chungan ; Yu, Dunshan ; Cao, Xixin ; Sheng, Shimin
刊名	jisuanji fuzhu sheji yu tuxingxue xuebaojournal of computer aided design and computer graphics
	2008
英文摘要	The hardware performance of H.264 macroblock-parallel VBSME SAD structure is discussed, and a novel pixel smoothing and resampling algorithm is proposed for hardware optimization. In this SAD algorithm, the current and reference pixels are partitioned into 2 ?? 2 subblocks, then smoothed and resampled for seven variable-block-size SAD calculations. It can effectively decrease the depth and width of cascaded adder for hardware reduction. Experimental results show that the proposed algorithm and its architecture can save over 53% hardware and power cost but only causes less than 1% RDO loss. It is very suitable for high-parallelism H. 264 VLSI solutions due to its excellent hardware performance.; EI; 0; 10; 1282-1287; 20
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/409125]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Peng, Chungan,Yu, Dunshan,Cao, Xixin,et al. H.264 VBSME SAD algorithm and architecture for hardware optimization[J]. jisuanji fuzhu sheji yu tuxingxue xuebaojournal of computer aided design and computer graphics,2008.
APA	Peng, Chungan,Yu, Dunshan,Cao, Xixin,&Sheng, Shimin.(2008).H.264 VBSME SAD algorithm and architecture for hardware optimization.jisuanji fuzhu sheji yu tuxingxue xuebaojournal of computer aided design and computer graphics.
MLA	Peng, Chungan,et al."H.264 VBSME SAD algorithm and architecture for hardware optimization".jisuanji fuzhu sheji yu tuxingxue xuebaojournal of computer aided design and computer graphics (2008).