Novel Sub-50 nm poly-Si gate patterning technology | |
Zhang, S.D. ; Han, R.Q. ; Liu, X.Y. ; Guan, X.D. ; Li, T. ; Zhang, D.C. | |
刊名 | pan tao ti hsueh paochinese journal of semiconductors
![]() |
2001 | |
英文摘要 | A novel low-cost sub-50 nm poly-Si gate patterning technology was proposed and experimentally demonstrated. The technology is resolution-independent, so that it does not contain any critical photolithographic step. The nano-scale masking pattern for gate formation is formed according to the image transfer of an edge-defined spacer. The experimental results reveal that the resultant gate length, about 75-85% of the thickness, is determined by the thickness of the film to form the spacer. From SEM photograph, the cross-section of the poly-Si gate is seen to be an inverted-trapezoid, which can be used to reduce the gate resistance.; EI; 0; 5; 565-568; 22 |
语种 | 英语 |
内容类型 | 期刊论文 |
源URL | [http://ir.pku.edu.cn/handle/20.500.11897/408349] ![]() |
专题 | 信息科学技术学院 |
推荐引用方式 GB/T 7714 | Zhang, S.D.,Han, R.Q.,Liu, X.Y.,et al. Novel Sub-50 nm poly-Si gate patterning technology[J]. pan tao ti hsueh paochinese journal of semiconductors,2001. |
APA | Zhang, S.D.,Han, R.Q.,Liu, X.Y.,Guan, X.D.,Li, T.,&Zhang, D.C..(2001).Novel Sub-50 nm poly-Si gate patterning technology.pan tao ti hsueh paochinese journal of semiconductors. |
MLA | Zhang, S.D.,et al."Novel Sub-50 nm poly-Si gate patterning technology".pan tao ti hsueh paochinese journal of semiconductors (2001). |
个性服务 |
查看访问统计 |
相关权益政策 |
暂无数据 |
收藏/分享 |
除非特别说明,本系统中所有内容都受版权保护,并保留所有权利。
修改评论