Folding and interpolating A/D converter with master-slave T/H circuit

CORC > 北京大学 > 信息科学技术学院

	Folding and interpolating A/D converter with master-slave T/H circuit
	Liu, Fei ; Jia, Song ; Lu, Zhenting ; Liu, Ling ; Ji, Lijiu
刊名	pan tao ti hsueh paochinese journal of semiconductors
	2004
英文摘要	A master-slave T/H circuit with the offset compensative amplifiers is proposed, which can improve sample precision and input bandwidth. A 250 Ms/s, 6-bit CMOS folding and interpolating A/D converter with M-S T/H is designed in a 1.2 ??m standard digital CMOS process. The simulation results demonstrate that the power dissipation of the converter is less than 300 mW for 5 V supply and the signal bandwidth is about 80 MHz. The latency between input and output is 2.5 clock cycles.; EI; 0; 4; 462-467; 25
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/407421]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Liu, Fei,Jia, Song,Lu, Zhenting,et al. Folding and interpolating A/D converter with master-slave T/H circuit[J]. pan tao ti hsueh paochinese journal of semiconductors,2004.
APA	Liu, Fei,Jia, Song,Lu, Zhenting,Liu, Ling,&Ji, Lijiu.(2004).Folding and interpolating A/D converter with master-slave T/H circuit.pan tao ti hsueh paochinese journal of semiconductors.
MLA	Liu, Fei,et al."Folding and interpolating A/D converter with master-slave T/H circuit".pan tao ti hsueh paochinese journal of semiconductors (2004).