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	A new approach for high performance multiply-accumulator design
	Lan, JH ; Li, LJ ; Jiang, AP ; Jia, S
	2003
关键词	parallel multiplier booth encoder partial product compression tree final addition CMOS circuit pass transistor logic
英文摘要	In our project of IP library creation, MAC is an important IP module. Here a new approach is proposed for designing high performance single cycle MAC. We combine the full custom design, gate level VHDL design and standard cell based synthesis together to get good performance and technology portability. After the technology is decided, basic circuit modules are custom designed and accurate hspice simulation is performed to generate exact driven, delay and area information. It is added to the standard cell library. We need to write the gate level HDL of a MAC using optimized special circuits, then apply logic synthesis. Then the structure and the interconnection of MAC have been decided by the gate level netlist, it can get the good performance of full custom design and have better portability. When being changed to a new technology, the designer only need to redesign the small circuits and simulate them, the gate level netlist needs not change. We compared the traditional 3-2 full adder, the redesigned 4-2 compressor. and the 9-2 compressor in this paper. The result is almost the same with the references. This new approach has advantages in IP reuse, shortens the developing times and can get the high performance of full custom design.; Computer Science, Hardware & Architecture; Engineering, Manufacturing; Engineering, Electrical & Electronic; CPCI-S(ISTP); 0
语种	英语
DOI标识	10.1109/ICASIC.2003.1277453
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/406950]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Lan, JH,Li, LJ,Jiang, AP,et al. A new approach for high performance multiply-accumulator design. 2003-01-01.

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