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	SSC Tracking Analysis and A Deeper-SSC Estimator
	Zhang, Yaming ; Gai, Weixin
	2013
关键词	CLOCK
英文摘要	This paper examines two kinds of bang-bang semidigital dual loop CDR architectures: 2nd-order and 3rd-order. Quantitative analysis is made in detail between the two in the presence of spread spectrum clocking (SSC) which hasn't been well studied. Moreover, a novel SSC estimator based on 3rd-order architecture is proposed to suppress the frequencyovershoot of conventional 3rd-order CDR happening at the switching points of SSC. The depth of its SSC tracking may be up to 10000ppm at 30 KHz which helps to reduce EMI.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000332006801161&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; EI; CPCI-S(ISTP); 1
语种	英语
DOI标识	10.1109/ISCAS.2013.6572119
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/405751]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhang, Yaming,Gai, Weixin. SSC Tracking Analysis and A Deeper-SSC Estimator. 2013-01-01.

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