QQ客服 官方微博 反馈留言

	Prefetching Techniques for STT-RAM based Last-level Cache in CMP Systems
	Mao, Mengjie ; Sun, Guangyu ; Li, Yong ; Jones, Alex K. ; Chen, Yiran
	2014
关键词	MEMORY PERFORMANCE ARCHITECTURE CIRCUIT MRAM
英文摘要	Prefetching is widely used in modern computer systems to mitigate the impact of long memory access latency by paying extra cost in memory and cache accesses. However, the efficacy of prefetching significantly degrades in the memory hierarchy using the emerging spin-transfer torque random access memory (STT-RAM) as last-level cache (LLC) due to the long write access latency. In this work, we propose two orthogonal but complimentary techniques to improve the prefetching efficacy of STT-RAM based LLC in chip multi-processor (CMP) systems, namely, request prioritization (RP) and hybrid local-global prefetch control (HLGPC). Simulation results show that by combining these two techniques, we can achieve 6.5%similar to 11% system performance improvement and 4.8%similar to 7.3% LLC energy saving in a quadcore system with a 2MB similar to 8MB STT-RAM based LLC, compared to the system with only basic prefetching.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000350791700019&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Computer Science, Hardware & Architecture; Computer Science, Software Engineering; EI; CPCI-S(ISTP); 2
语种	英语
DOI标识	10.1109/ASPDAC.2014.6742868
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/405585]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Mao, Mengjie,Sun, Guangyu,Li, Yong,et al. Prefetching Techniques for STT-RAM based Last-level Cache in CMP Systems. 2014-01-01.

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。