An energy-efficient instruction scheduler design with two-level shelving   and adaptive banking

doi:10.1007/s11390-007-9001-2

CORC > 北京大学 > 信息科学技术学院

	An energy-efficient instruction scheduler design with two-level shelving and adaptive banking
	Zhao, Yu-Lai ; Li, Xian-Feng ; Tong, Dong ; Cheng, Xu
刊名	计算机科学技术学报英文版
	2007
关键词	content associative memory (CAM) energy-efficient architecture instruction scheduler tag elimination waiting instruction buffer
DOI	10.1007/s11390-007-9001-2
英文摘要	Mainstream processors implement the instruction scheduler using a monolithic CAM-based issue queue (IQ), which consumes increasingly high energy as its size scales. In particular, its instruction wakeup logic accounts for a major portion of the consumed energy. Our study shows that instructions with 2 non-ready operands (called 2OP instructions) are in small percentage, but tend to spend long latencies in the IQ. They can be effectively shelved in a small RAM-based waiting instruction buffer (WIB) and steered into the IQ at appropriate time. With this two-level shelving ability, half of the CAM tag comparators are eliminated in the IQ, which significantly reduces the energy of wakeup operation. In addition, we propose an adaptive banking scheme to downsize the IQ and reduce the bit-width of tag comparators. Experiments indicate that for an 8-wide issue superscalar or SMT processor, the energy consumption of the instruction scheduler can be reduced by 67%. Furthermore, the new design has potentially faster scheduler clock speed while maintaining close IPC to the monolithic scheduler design. Compared with the previous work on eliminating tags through prediction, our design is superior in terms of both energy reduction and SMT support.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000243890200002&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Computer Science, Hardware & Architecture; Computer Science, Software Engineering; SCI(E); EI; 中国科技核心期刊(ISTIC); 中国科学引文数据库(CSCD); 2; ARTICLE; 1; 15-24; 22
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/398070]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhao, Yu-Lai,Li, Xian-Feng,Tong, Dong,et al. An energy-efficient instruction scheduler design with two-level shelving and adaptive banking[J]. 计算机科学技术学报英文版,2007.
APA	Zhao, Yu-Lai,Li, Xian-Feng,Tong, Dong,&Cheng, Xu.(2007).An energy-efficient instruction scheduler design with two-level shelving and adaptive banking.计算机科学技术学报英文版.
MLA	Zhao, Yu-Lai,et al."An energy-efficient instruction scheduler design with two-level shelving and adaptive banking".计算机科学技术学报英文版 (2007).