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	An efficient and flexible host-FPGA PCIe communication library
	Gong, Jian ; Wang, Tao ; Chen, Jiahua ; Wu, Haoyang ; Ye, Fan ; Lu, Songwu ; Cong, Jason
	2014
英文摘要	A high-performance interconnection between a host processor and FPGA accelerators is in much demand. Among various interconnection methods, a PCIe bus is an attractive choice for loosely coupled accelerators. Because there is no standard host-FPGA communication library, FPGA developers have to write significant amounts of PCIe related code at both the FPGA side and the host processor side. A high-performance host-FPGA PCIe communication library holds the key to broadening the use of FPGA accelerators. In this paper we target efficiency and flexibility as two important features in such a library. We discuss the challenges in providing these features, and present our solution to these challenges. We propose EPEE, an efficient and flexible host-FPGA PCIe communication library and describe its design. We implemented EPEE in various generations of Xilinx FPGAs with up to 26.24 Gbps half-duplex and 43.02 Gbps full-duplex aggregate throughput in the PCIe Gen2 X8 mode; these are at the best utilization levels that a host-FPGA PCIe library can achieve. The EPEE library has been integrated into four different FPGA applications with different data usage patterns in various institutes.; EI; 0
语种	英语
DOI标识	10.1109/FPL.2014.6927459
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/329413]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Gong, Jian,Wang, Tao,Chen, Jiahua,et al. An efficient and flexible host-FPGA PCIe communication library. 2014-01-01.

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