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	Demonstration of memory string with stacked junction-less SONOS realized on vertical silicon nanowire
	Sun, Y. ; Yu, H.Y. ; Singh, N. ; Leong, K.C. ; Quek, E. ; Lo, G.Q. ; Kwong, D.L.
	2011
英文摘要	We demonstrated a NAND memory string based on 2-level stacked junction-less (JL) gate-all-around (GAA) SONOS cells fabricated on vertical Si nanowire (SiNW) platform with footprint of 6F2/2. The stacked SiNW memory cells with channel dimension down to 30nm exhibit well-behaved memory characteristics such as program/erase (P/E) speeds, endurance, retention and program disturb properties. The vertically stacked device structure improves the bit density and the absence of junctions reduces the process complexity/cost and makes this device manufacturable with very low thermal budget. ? 2011 IEEE.; EI; 0
语种	英语
DOI标识	10.1109/IEDM.2011.6131524
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/328635]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Sun, Y.,Yu, H.Y.,Singh, N.,et al. Demonstration of memory string with stacked junction-less SONOS realized on vertical silicon nanowire. 2011-01-01.

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