Area saved and clamp efficient multi-RC-triggered power clamp circuit for on-chip ESD protection | |
Guo, Haibing ; Wang, Yuan ; Lu, Guangyi ; Jia, Song ; Zhang, Xing | |
2014 | |
英文摘要 | An improved multi-RC-triggered power clamp circuit is presented in this paper. It could save more silicon area than prior designs while clamp the VDD more efficiently. The three-stage RC-trigger circuit design can fast close up the clamp MOSFET when it is mis-triggered in a certain situation. Mis-trigger immunity down to 2??s power-up rise time is also achieved for a designed clamp MOSFET width of 1920??m. ? 2014 IEEE.; EI; 0 |
语种 | 英语 |
DOI标识 | 10.1109/ICSICT.2014.7021665 |
内容类型 | 其他 |
源URL | [http://ir.pku.edu.cn/handle/20.500.11897/295571] ![]() |
专题 | 信息科学技术学院 |
推荐引用方式 GB/T 7714 | Guo, Haibing,Wang, Yuan,Lu, Guangyi,et al. Area saved and clamp efficient multi-RC-triggered power clamp circuit for on-chip ESD protection. 2014-01-01. |
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