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	Investigation on the effective immunity to process induced line-edge roughness in silicon nanowire MOSFETs
	Yu, Tao ; Ding, Wei ; Zhuge, Jing ; Zhang, Liangliang ; Wang, Runsheng ; Ru, Huang
	2010
英文摘要	The silicon nanowire MOSFET (SNWT) with gate-all-around (GAA) architecture has exhibited great potential in high-performance nano-electronics applications [1-4]. However, line-edge roughness (LER) induced by lithography and etching processes has become a critical concern for decananometer MOSFETs, because it does not scale accordingly with line widths [5]. Especially, the LER of nanowires, which contains two degrees of freedom rather than one in the traditional planar devices, may have different and intriguing effect on SNWTs. Therefore, performance variation of SNWTs induced by nanowire-LER may become a great challenge to scalability and stability of SNWT-based ICs, where 2-D geometrical fluctuation becomes an even more serious problem in nano-scale. Yet, only few preliminary studies on such impact have been reported [6]. In this paper, a full 3-D statistical investigation is performed, based on the measured LER from SEM images, to estimate the impact of nanowire-LER on SNWTs, including both DC and analog/RF performance. The results can provide guidelines for process optimization as well as robust design of SNWT-based circuits. ? 2010 IEEE.; EI; 0
语种	英语
DOI标识	10.1109/VTSA.2010.5488962
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/295539]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Yu, Tao,Ding, Wei,Zhuge, Jing,et al. Investigation on the effective immunity to process induced line-edge roughness in silicon nanowire MOSFETs. 2010-01-01.

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