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	A 14-bit 300MHz pipelined DEM DAC with enhanced dynamic linearity
	Junlei, Zhao ; Yuan, Wang ; Zhihui, Zhao ; Song, Jia
	2010
英文摘要	This paper presents a 14-bit digital-to-analog converter (DAC) with pipelined dynamic element matching to eliminate signal-dependent distortions and achieve good linearity at high sampling frequencies. A return-to-zero output stage is developed to enhance the dynamic linearity and increase the output impedance of current sources. And a novel current source array is employed to eliminate systematic and graded errors. The spurious-free dynamic range is 80.9dB at 312MS/s with a 150MHz input. The DAC is implemented in a 0.13-??m CMOS process, and consumes 48mW at 1.2-V power supply and 312MS/s.; EI; 0
语种	英语
DOI标识	10.1109/PRIMEASIA.2010.5604954
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/295401]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Junlei, Zhao,Yuan, Wang,Zhihui, Zhao,et al. A 14-bit 300MHz pipelined DEM DAC with enhanced dynamic linearity. 2010-01-01.

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