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	Effective design for crff sigma-delta modulators using inverters based on 0.13m CMOS
	Li, Hongyi ; Wang, Yuan ; Jia, Song ; Zhang, Xing
	2011
英文摘要	In this paper, an efficient method to relax timing requirements of CRFF sigma-delta modulators has been proposed. A system optimization to circuit level design was finished. Class-C inverter was used to realize half delay integrators of the proposed structure. A 4th-order 1-bit CRFF topology was implemented in smic 0.13??m CMOS technology. With 31.25MHz sampling frequency and 64x oversampling ratio, 13.2-bit resolution has been reached. The whole circuit consumes 472.63-??W power from a single 0.6V supply voltage. Thus, a low-voltage low-power medium-bandwidth high-accuracy sigma-delta modulator has been obtained. ? 2011 Springer-Verlag Berlin Heidelberg.; EI; 0
语种	英语
DOI标识	10.1007/978-3-642-19712-3-72
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/295388]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Li, Hongyi,Wang, Yuan,Jia, Song,et al. Effective design for crff sigma-delta modulators using inverters based on 0.13m CMOS. 2011-01-01.

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