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	Design of the fast aequisition PLL with wide tuning range
	Yan, Ge ; Song, Jia ; Lijiu, Ji
	2007
英文摘要	In this paper we present a design of adaptive gain phase-locked loop (PLL) which features fast acquisition, low jitter and wide tuning range. A dual-edge-triggered phase frequency detector (PFD) and a self-regulated voltage controlled oscillator (VCO) are employed in this design to realize the aforementioned properties. The measured results show that the experimental chip with a standard logic 0.5-??m 5V CMOS process has the acquisition time less than 150ns@37% frequency variation and output rms jitter of 23ps@640MHz. ? 2006 IEEE.; EI; 0
语种	英语
DOI标识	10.1109/ICSICT.2006.306584
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/295131]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Yan, Ge,Song, Jia,Lijiu, Ji. Design of the fast aequisition PLL with wide tuning range. 2007-01-01.

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