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	Stacked-cascode Class-E power amplifier with delay-controlled auxiliary branches in 65nm CMOS
	Yang, Fan ; Liao, Yu ; Xia, Tao ; Wang, Runhua ; Huang, Ru ; Liao, Huailin
	2014
英文摘要	Low breakdown voltage in deep-submicron CMOS devices has limited the supply voltage and output power of power amplifiers (PAs). In this paper, a differential cascode Class-E PA in 65nm CMOS is proposed. Using only the standard devices, the stacked-cascode structure can endure a maximum voltage up to 10V so that a supply voltage of 3.3V is possible for Class-E PA. An auxiliary branch is added to reduce the turn-on resistance. With an inductor to delay the control signal phase of the branch, the proposed PA has a power dissipation trade-off between the devices' on/off state. At 1.6GHz, the proposed Class-E PA achieves Power Added Efficiency (PAE) of 57.5% when it transmits 31.3dBm power. ? 2014 IEEE.; EI; 0
语种	英语
DOI标识	10.1109/ICSICT.2014.7021516
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/294797]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Yang, Fan,Liao, Yu,Xia, Tao,et al. Stacked-cascode Class-E power amplifier with delay-controlled auxiliary branches in 65nm CMOS. 2014-01-01.

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