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	A novel low jitter PLL clock generator with supply noise insensitive design
	Lin, Yijing ; Sheng, Shimin
	2001
英文摘要	A novel control circuit is proposed to suppress the jitter caused by high frequency noise, which spectrum is beyond the loop bandwidth of the PLL used as clock generator in an USB2.0 application. Hspice simulates the circuits with BSIM3V3 model, and the cycle-to-cycle jitter is 1.68ps when the VDD noise is 200mv, 10MHz square wave.; EI; 0
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/294780]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Lin, Yijing,Sheng, Shimin. A novel low jitter PLL clock generator with supply noise insensitive design. 2001-01-01.

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