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	Design of D flip-flops with low power-delay product based on FinFET
	Liao, Kai ; Cui, Xiaoxin ; Liao, Nan ; Wang, Tian
	2014
英文摘要	In this paper, FinFET has been introduced to the design of high performance D flip-flops. Based on the excellent electrical properties of FinFET, the SG-mode D flip-flop modified from original PHLFF by substituting SG-mode FinFET for planar MOSFET has a tremendous reduction of 87.0% on power-delay product (PDP). Considering the unique merits of multiple operating modes of FinFET, further optimization based on SG-mode PHLFF has been proposed to achieve lower PDP and more efficient area utilization rate. The simulation results indicate that the multi-mode PHLFF reduces the PDP by 92.6% and slightly decreases the number of transistors. ? 2014 IEEE.; EI; 0
语种	英语
DOI标识	10.1109/ICSICT.2014.7021366
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/294768]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Liao, Kai,Cui, Xiaoxin,Liao, Nan,et al. Design of D flip-flops with low power-delay product based on FinFET. 2014-01-01.

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