Simulation of correlated line-edge roughness in multi-gate devices | |
Jiang, Xiaobo ; Wang, Runsheng ; Huang, Ru ; Chen, Jiang | |
2013 | |
英文摘要 | In this paper, the impacts of correlated line-edge roughness (LER) are investigated. Experimental statistics indicate that, the LER of the two edges in Si channel (Fin or nanowire) have strong cross-correlation, depending on the fabrication process. An improved simulation method based on Fourier synthesis is used to generate pairs of LER sequences with certain cross-correlation. The results show that, device Vth distribution is strongly dependent on the cross-correlation, and can exhibit non-Gaussian distribution. Dual-peak distribution appears and enlarges the variation of Vth significantly. In addition, a new method to extend 2D LER into 3D LER is proposed for future LER investigation. ? 2013 IEEE.; EI; 0 |
语种 | 英语 |
DOI标识 | 10.1109/SISPAD.2013.6650590 |
内容类型 | 其他 |
源URL | [http://ir.pku.edu.cn/handle/20.500.11897/294420] ![]() |
专题 | 信息科学技术学院 |
推荐引用方式 GB/T 7714 | Jiang, Xiaobo,Wang, Runsheng,Huang, Ru,et al. Simulation of correlated line-edge roughness in multi-gate devices. 2013-01-01. |
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