QQ客服 官方微博 反馈留言

	Static CMOS hnplementation of Logarithmic Skip Adder
	Jia, S ; Liu, F ; Gao, J ; Liu, L ; Wang, X ; Zhang, T ; Chen, ZJ ; Ji, LJ
	2003
关键词	PARALLEL ADDERS
英文摘要	Circuit design of 32-bit Logarithmic Skip Adder (LSA) is introduced to implement high performance, low power addition. At architecture level, ELM carry lookahead adder is included into blocks of carry skip adder and the hybrid architecture of LSA costs 30% less hardware than ELM. At circuit level carry-incorporating structure to include the primary carry input in carry chain and and-xor structure to implement final sum logic are designed. Circuit simulation using spectre simulator are presented and compared with recent literatures'. For 2.5v, 0.25um process, critical delay of 0.8ns, power dissipation of 5.2mw at 100MHz is simulated.; Engineering, Electrical & Electronic; Optics; Physics, Condensed Matter; CPCI-S(ISTP); 0
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/293851]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Jia, S,Liu, F,Gao, J,et al. Static CMOS hnplementation of Logarithmic Skip Adder. 2003-01-01.

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。