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	Scalability and reliability of TaN/HfN/HfO(2) gate stacks fabricated by a high temperature process
	Kang, JF ; Yu, HY ; Ren, C ; Yang, H ; Sa, N ; Liu, XY ; Han, RQ ; Li, MF ; Chan, DSH ; Kwong, DL
	2005
英文摘要	The scalability and reliability issues of the CVD-HfO(2) gate dielectrics with PVD TaN/HfN electrodes, fabricated by a high temperature process, were addressed. The equivalent oxide thickness (EOT) is aggressively scaled down to 0.75 nm and 0.95 nm for MOS capacitor and MOSFET, respectively. Low preexisting traps in the TaN/HfN/HfO(2) gate stacks were observed, which could be attributed to the high temperature post gate annealing process. The excellent reliability characteristics were achieved in the TaN/HfN/HfO(2) gate stacks.; Engineering, Electrical & Electronic; Instruments & Instrumentation; Physics, Condensed Matter; EI; CPCI-S(ISTP); 0
语种	英语
DOI标识	10.1109/ESSDER.2005.1546663
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/293660]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Kang, JF,Yu, HY,Ren, C,et al. Scalability and reliability of TaN/HfN/HfO(2) gate stacks fabricated by a high temperature process. 2005-01-01.

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