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	Low Power Folding/Interpolating ADC with a Novel Dynamic Encoder Based on ROM Theory
	Yin, Jilei ; Wang, Yuan ; Jia, Song ; Liu, Zhen
	2008
英文摘要	A 6-bit 200Msps Folding/Interpolating analog to digital converter (ADC) with a novel dynamic encoder based on Rom theory is presented. The Precharge & Evaluate dynamic circuit is employed in the novel encoder and the bit synchronization logic to achieve high speed and reduce power dissipation. Realized in SMIC 0.35um digital CMOS process, the whole ADC consumes only 35mW at a 3.3V voltage supply.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000265971003016&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; Physics, Applied; EI; CPCI-S(ISTP); 0
语种	英语
DOI标识	10.1109/ICSICT.2008.4734947
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/293446]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Yin, Jilei,Wang, Yuan,Jia, Song,et al. Low Power Folding/Interpolating ADC with a Novel Dynamic Encoder Based on ROM Theory. 2008-01-01.

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