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	A 10-b 80Ms/s time-interleaved pipeline ADC using partially opamp sharing scheme
	Cao Junmin ; Chen Zhongjian ; Lu Wengao ; Zhao Baoying
	2007
英文摘要	A 10-bit 80MS/s two-channel time-interleaved pipeline analog-digital converter is presented. Nonlinearity and Mismatch between the channels are minimized by applying partially opamp sharing scheme. And a dedicated double-sampling SHA is employed to eliminate time skew between the channels. The converter architecture is also optimized for power dissipation by employing dynamic comparator and stage scaling down technology. Simulated with 0.5um technology, the ADC dissipates 210mw of power from a 5v supply, and achieves a peak SNDR of 56dB at 80Ms/s.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000253449900061&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; CPCI-S(ISTP); 0
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/293305]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Cao Junmin,Chen Zhongjian,Lu Wengao,et al. A 10-b 80Ms/s time-interleaved pipeline ADC using partially opamp sharing scheme. 2007-01-01.

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