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	Simulation of Line-Edge Roughness Effects in Silicon Nanowire MOSFETs
	Yu, Tao ; Wang, Runsheng ; Huang, Ru
	2010
关键词	CMOS TECHNOLOGY INTEGRATION PERFORMANCE TRANSISTORS
英文摘要	In this paper, the effects of nanowire (NW) lineedge roughness (LER) in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) are investigated by 3-D statistical simulation in terms of both performance variation and mean value degradation. A physical model is developed for NW LER induced performance degradation in SNWTs for the first time. The results indicate large performance mean value degradations due to NW LER in SNWTs. However, the LER induced parameter variation is still acceptable. In addition, as the LER correlation length (Lambda) scales beyond the gate length, new distribution of performance parameters is observed, which has dual-peaks rather than single in conventional Gaussian distribution. The optimization for NW LER parameters is given for SNWT design as well.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000283778800030&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; Physics, Applied; EI; CPCI-S(ISTP); 0
语种	英语
DOI标识	10.1109/SISPAD.2010.5604534
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/293060]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Yu, Tao,Wang, Runsheng,Huang, Ru. Simulation of Line-Edge Roughness Effects in Silicon Nanowire MOSFETs. 2010-01-01.

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