Low-power, high-speed dual modulus prescalers based on branch-merged   true single-phase clocked scheme

doi:10.1049/el.2014.4146

CORC > 北京大学 > 信息科学技术学院

	Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme
	Jia, Song ; Yan, Shilin ; Wang, Yuan ; Zhang, Ganggang
刊名	electronics letters
	2015
关键词	analogue-digital conversion digital-analogue conversion energy-efficient capacitor-splitting DAC scheme SAR ADC accuracy digital-to-analogue converter successive approximation register analogue-to-digital converter split-capacitive-array DAC structure energy-efficient-up transition switching energy reduction area reduction third-reference voltage least significant bit FREQUENCY-DIVIDER
DOI	10.1049/el.2014.4146
英文摘要	A new design scheme intended to improve the performance of true single-phase clocked (TSPC) dual modulus prescalers is presented. Two branches of TSPC D flip-flops are merged to reduce both power and device count. An HSPICE simulation of the proposed scheme demonstrates the highest power efficiency and best power-delay product among the referenced designs.; Engineering, Electrical & Electronic; SCI(E); EI; 0; ARTICLE; jias@pku.edu.cn; 6; 464-465; 51
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/291476]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Jia, Song,Yan, Shilin,Wang, Yuan,et al. Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme[J]. electronics letters,2015.
APA	Jia, Song,Yan, Shilin,Wang, Yuan,&Zhang, Ganggang.(2015).Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme.electronics letters.
MLA	Jia, Song,et al."Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme".electronics letters (2015).