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	A high-speed dual field arithmetic unit and hardware implementation
	Jian, Wang ; Anping, Jiang
	2007
英文摘要	Finite fields have been used for many types of Public Key Cryptography, such as Elliptic Curve (EC) and RSA Cryptosystems. This paper presents an arithmetic unit that support Galois fields GF(p) and GF(2m) for arbitrary prime numbers and irreducible polynomials respectively. The arithmetic unit can do the Galois field arithmetic operations of addition, subtraction, multiplication, squaring, inversion and division. The least significant bit first (LSB-first) scheme for modular multiplication and the extended Euclid's algorithm for modular inversion are both modified for the arithmetic unit. The architecture has been implemented using 0.18-??m CMOS standard cell library, the clock frequency can reach at least 250MHz for a 256-bit arithmetic unit. Furthermore, any bit length can be supported by any hardware configuration so long as the memory capacity is sufficient. ? 2007 IEEE.; EI; 0
语种	英语
DOI标识	10.1109/ICASIC.2007.4415605
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/263349]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Jian, Wang,Anping, Jiang. A high-speed dual field arithmetic unit and hardware implementation. 2007-01-01.

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