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Unified physical I-V model of fully depleted SOI/MOSFETs for analog digital circuit simulation
Cheng, YH ; Fjeldly, TA
刊名固体电子学
1996
关键词SOI MOSFETS THRESHOLD VOLTAGE TRANSISTORS DEVICE
DOI10.1016/0038-1101(95)00184-0
英文摘要An improved physical I-V model for fully depleted SOI/MOSFETs with channel lengths down to deep submicrometer range is presented. The model contains the following advanced features: precise description of the subthreshold, near-threshold and above-threshold regimes of operation using one single expression; precise description of I-V and G-V characteristics in the saturation region; continuous and smooth transition of the drain current and conductance from the linear to the saturation regime; extrinsic model expressions for devices with parasitic drain and source series resistances; inclusion of important short channel effects accounting for velocity saturation, drain induced barrier lowering (DIBL) and drain induced conductivity enhancement (DICE), channel length modulation (CLM), as well as the gate bias dependent mobility; a description of the floating body effect associated with drain breakdown. Inclusion of these features greatly improves the accuracy as well as the convergence properties and the calculating efficiency when using the model in;circuit simulators. The present model agrees well with experimental results for a wide range of process and device parameters.; Engineering, Electrical & Electronic; Physics, Applied; Physics, Condensed Matter; SCI(E); 6; ARTICLE; 5; 721-730; 39
语种英语
内容类型期刊论文
源URL[http://ir.pku.edu.cn/handle/20.500.11897/258414]  
专题信息科学技术学院
推荐引用方式
GB/T 7714
Cheng, YH,Fjeldly, TA. Unified physical I-V model of fully depleted SOI/MOSFETs for analog digital circuit simulation[J]. 固体电子学,1996.
APA Cheng, YH,&Fjeldly, TA.(1996).Unified physical I-V model of fully depleted SOI/MOSFETs for analog digital circuit simulation.固体电子学.
MLA Cheng, YH,et al."Unified physical I-V model of fully depleted SOI/MOSFETs for analog digital circuit simulation".固体电子学 (1996).
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