A three-dimensional stacked Fin-CMOS technology for high-density ULSI   circuits

doi:10.1109/TED.2005.854267

CORC > 北京大学 > 信息科学技术学院

	A three-dimensional stacked Fin-CMOS technology for high-density ULSI circuits
	Wu, XS ; Chan, PCH ; Zhang, SD ; Feng, CG ; Chan, M
刊名	ieee电子器件汇刊
	2005
关键词	CMOSFET FinFET silicon-on-insulator (SOI) three-dimensional integrated circuits (3-D IC) GATE
DOI	10.1109/TED.2005.854267
英文摘要	In this paper, a three-dimensional CMOS technology is proposed and implemented using stacked Fin-CMOS (SF-CMOS) architecture. The technology is based on a double layer silicon-on-insulator wafer formed by two oxygen implants to create two single-crystal silicon films with an oxide isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of the wiring distance between active devices through vertical connection when compared with conventional planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET structure. SF-CMOS devices and simple circuits were fabricated and characterized.; Engineering, Electrical & Electronic; Physics, Applied; SCI(E); EI; 5; ARTICLE; 9; 1998-2003; 52
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/253081]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Wu, XS,Chan, PCH,Zhang, SD,et al. A three-dimensional stacked Fin-CMOS technology for high-density ULSI circuits[J]. ieee电子器件汇刊,2005.
APA	Wu, XS,Chan, PCH,Zhang, SD,Feng, CG,&Chan, M.(2005).A three-dimensional stacked Fin-CMOS technology for high-density ULSI circuits.ieee电子器件汇刊.
MLA	Wu, XS,et al."A three-dimensional stacked Fin-CMOS technology for high-density ULSI circuits".ieee电子器件汇刊 (2005).