Data Memory Subsystem Resilient to Process Variations

doi:10.1109/TVLSI.2008.2001299

CORC > 北京大学 > 信息科学技术学院

	Data Memory Subsystem Resilient to Process Variations
	Bennaser, Mahmoud ; Guo, Yao ; Moritz, Csaba Andras
刊名	ieee transactions on very large scale integration vlsi systems
	2008
关键词	CMOS memory integrated circuits memory architecture process variations PARAMETER FLUCTUATIONS IMPACT CMOS
DOI	10.1109/TVLSI.2008.2001299
英文摘要	As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance of processors by making the latency of circuits less predictable and thus requiring conservative design approaches. In this paper, we use Monte Carlo simulations in addition to worst-case circuit analysis to establish the overall delay due to process variations in a data cache sub-system under both typical and worst-case conditions. The distribution of the cache critical-path-delay in the typical scenario was determined by performing Monte Carlo simulations at different supply voltages, threshold voltages, and transistor lengths on a complete cache design. In addition to establishing the delay variation, we present an adaptive variable-cycle-latency cache architecture that mitigates the impact of process variations on access latency by closely following the typical latency behavior rather than assuming a conservative worst-case design-point. Simulation results show that our adaptive data cache can achieve a 9% to 31% performance improvement in a superscalar processor, on the SPEC2000 applications studied, compared to a conventional design. The area overhead for the additional circuits of the adaptive technique has less than 1% of the total cache area. Additional performance improvement potential exists in processors where the data cache access is on the critical path, by allowing a more aggressive clock rate.; Computer Science, Hardware & Architecture; Engineering, Electrical & Electronic; SCI(E); EI; 1; ARTICLE; 12; 1631-1638; 16
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/247827]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Bennaser, Mahmoud,Guo, Yao,Moritz, Csaba Andras. Data Memory Subsystem Resilient to Process Variations[J]. ieee transactions on very large scale integration vlsi systems,2008.
APA	Bennaser, Mahmoud,Guo, Yao,&Moritz, Csaba Andras.(2008).Data Memory Subsystem Resilient to Process Variations.ieee transactions on very large scale integration vlsi systems.
MLA	Bennaser, Mahmoud,et al."Data Memory Subsystem Resilient to Process Variations".ieee transactions on very large scale integration vlsi systems (2008).