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	A cost-efficient 12-bit 20Msamples/s pipelined ADC
	Junmin, Cao ; Zhongjian, Chen ; Wengao, Lu ; Baoying, Zhao
	2008
英文摘要	A 12-bit 20MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5um CMOS technology, the ADC dissipates 65mw from a 5V supply, and achieves a peak SNDR of 70.1dB with a 1MHz full-scale sine input at 20MS/s. ?2008 IEEE.; EI; 0
语种	英语
DOI标识	10.1109/ICSICT.2008.4734945
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/153628]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Junmin, Cao,Zhongjian, Chen,Wengao, Lu,et al. A cost-efficient 12-bit 20Msamples/s pipelined ADC. 2008-01-01.

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