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	A Low Power 12-Bit 20Msamples/s Pipelined ADC
	Cao Junmin ; Chen Zhongjian ; Lu Wengao ; Zhao Baoying
	2009
关键词	CMOS ADC 10-BIT
英文摘要	A 12-bit 20MS/s low power pipelined analog-digital converter is presented. A front-end sampling network is proposed to eliminate the need of SHA. Passive capacitor error-averaging technique (PCEA) and Opamp sharing scheme are employed to achieve high resolutions and low power and area. The drawback of conventional Opamp sharing technique is resolved with polarity inverting scheme by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5um mix-signal CMOS technology, the ADC dissipates 71mw from a 5V supply, and achieves a peak SNDR of 69.8dB with a 0.5MHz full-scale sine input at 20MS/s.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000275782600016&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; EI; CPCI-S(ISTP); 0
语种	英语
DOI标识	10.1109/ICSPS.2009.16
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/153344]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Cao Junmin,Chen Zhongjian,Lu Wengao,et al. A Low Power 12-Bit 20Msamples/s Pipelined ADC. 2009-01-01.

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