A compact SOI MOS transistor model for distortion analysis

doi:10.1016/S0038-1101(02)00269-1

CORC > 北京大学 > 信息科学技术学院

	A compact SOI MOS transistor model for distortion analysis
	Zhang, GY ; Liao, HL ; Huang, R ; Chan, MS ; Zhang, X ; Wang, YY
刊名	固体电子学
	2003
关键词	distortion analysis SOI MOSFET MOSFET model CIRCUIT SIMULATION
DOI	10.1016/S0038-1101(02)00269-1
英文摘要	SOI technology is now emerging as a mature technology applied in the analog IC design, which necessities an accurate model to describe distortion effects. In this paper a compact transistor model is proposed for distortion analysis of fully depleted SOI MOSFET operating in strong inversion regime. In the model, both short channel effects and self-heating effect (unique to SOI due to the buried oxide) are considered. To obtain a concise and accurate model an approximation method is developed to determine the dominant physical effects in distortion analysis. The model agrees well with the experimental data. (C) 2002 Elsevier Science Ltd. All rights reserved.; Engineering, Electrical & Electronic; Physics, Applied; Physics, Condensed Matter; SCI(E); EI; 2; ARTICLE; 1; 143-147; 47
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/153118]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhang, GY,Liao, HL,Huang, R,et al. A compact SOI MOS transistor model for distortion analysis[J]. 固体电子学,2003.
APA	Zhang, GY,Liao, HL,Huang, R,Chan, MS,Zhang, X,&Wang, YY.(2003).A compact SOI MOS transistor model for distortion analysis.固体电子学.
MLA	Zhang, GY,et al."A compact SOI MOS transistor model for distortion analysis".固体电子学 (2003).