A stacked CMOS technology on SOI substrate

doi:10.1109/LED.2004.834735

CORC > 北京大学 > 信息科学技术学院

	A stacked CMOS technology on SOI substrate
	Zhang, SD ; Han, RQ ; Lin, XN ; Wu, XS ; Chan, MS
刊名	ieee electron device letters
	2004
关键词	double-gate self-alignment SOICMOS 3-D integration
DOI	10.1109/LED.2004.834735
英文摘要	A stacked CMOS technology fabricated on semic conductor-on-insulator (SOI) wafers with the p-MOSFET on the SOI film and the n-MOSFET on the bulk substrate is demonstrated. The technology provides a number of advantages, including: 1) single crystal multi-layer of active devices; 2) self-aligned double-gate p-MOSFET with thick source/drain and thin channel regions; 3) self-aligned channel region of n-MOSFET to p-MOSFET stacked perfectly on top of each other; 4) significant area saving; and 5) reduced interconnect distance and loading. Experimental results show that the fabricated double-gate p-MOSFET has a nearly ideal subthreshold swing and almost the same current drive as the n-MOSFET with the same lateral width, resulting in a highly compact and completely overlap stacked CMOS inverter.; Engineering, Electrical & Electronic; SCI(E); EI; 4; ARTICLE; 9; 661-663; 25
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/153077]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhang, SD,Han, RQ,Lin, XN,et al. A stacked CMOS technology on SOI substrate[J]. ieee electron device letters,2004.
APA	Zhang, SD,Han, RQ,Lin, XN,Wu, XS,&Chan, MS.(2004).A stacked CMOS technology on SOI substrate.ieee electron device letters.
MLA	Zhang, SD,et al."A stacked CMOS technology on SOI substrate".ieee electron device letters (2004).