An area-efficient FFT architecture for OFDM digital video broadcasting

doi:10.1109/TCE.2007.4429219

CORC > 北京大学 > 信息科学技术学院

	An area-efficient FFT architecture for OFDM digital video broadcasting
	Jiang, Richard A.
刊名	ieee transactions on consumer electronics
	2007
关键词	OFDM demodulation FFT DVB-T HDTV IMPLEMENTATION PROCESSOR ALGORITHM CHIP
DOI	10.1109/TCE.2007.4429219
英文摘要	In this paper, a novel high-performance 8k-point fast Fourier transform(DFT) processor architecture for OFDM digital video broadcasting(DVB) is proposed based on a novel radix-8 FFT architecture. Distributed arithmetic(DA) is used to implement the basic 8-point FFTs directly, where the hardware cost of complex multipliers and adders can be greatly reduced. The twiddle multiplications are performed by CORDIC-based twiddle multipliers. The results show that the proposed processor architecture can greatly save the area cost while keeping a high-speed processing speed, which may be attractive for many real-time DVB-T systems(1).; Engineering, Electrical & Electronic; Telecommunications; SCI(E); EI; 16; ARTICLE; 4; 1322-1326; 53
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/153040]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Jiang, Richard A.. An area-efficient FFT architecture for OFDM digital video broadcasting[J]. ieee transactions on consumer electronics,2007.
APA	Jiang, Richard A..(2007).An area-efficient FFT architecture for OFDM digital video broadcasting.ieee transactions on consumer electronics.
MLA	Jiang, Richard A.."An area-efficient FFT architecture for OFDM digital video broadcasting".ieee transactions on consumer electronics (2007).