Investigations on Line-Edge Roughness (LER) and Line-Width Roughness   (LWR) in Nanoscale CMOS Technology: Part I-Modeling and Simulation   Method

doi:10.1109/TED.2013.2283518

CORC > 北京大学 > 信息科学技术学院

	Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part I-Modeling and Simulation Method
	Jiang, Xiaobo ; Wang, Runsheng ; Yu, Tao ; Chen, Jiang ; Huang, Ru
刊名	ieee电子器件汇刊
	2013
关键词	Auto-correlation function cross-correlation line-edge-roughness (LER) line-width-roughness (LWR) modeling variability INTRINSIC PARAMETER FLUCTUATIONS VARIABILITY MOSFETS DECANANOMETER PERFORMANCE
DOI	10.1109/TED.2013.2283518
英文摘要	In this paper, the correlation between line-edge roughness (LER) and line-width roughness (LWR) is investigated. Based on the characterization methodology of auto-correlation functions (ACF), a new theoretical model of LWR is proposed, which indicates that the LWR ACF is composed of two parts: one involves LER information; the other involves the cross-correlation of the two edges. Additional characteristic parameters for LER/LWR are proposed to represent the missing cross-correlation information in conventional approaches of LER/LWR description, other than LER/LWR amplitude and auto-correlation length. An improved simulation method for correlated LERs is also proposed, which can provide helpful guidelines for the characterization, modeling, and the optimization of LER/LWR in nanoscale CMOS technology. The experimental results and device simulation results are discussed in detail in the part II of this paper.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000326263200009&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; Physics, Applied; SCI(E); EI; 13; ARTICLE; 11; 3669-3675; 60
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/152234]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Jiang, Xiaobo,Wang, Runsheng,Yu, Tao,et al. Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part I-Modeling and Simulation Method[J]. ieee电子器件汇刊,2013.
APA	Jiang, Xiaobo,Wang, Runsheng,Yu, Tao,Chen, Jiang,&Huang, Ru.(2013).Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part I-Modeling and Simulation Method.ieee电子器件汇刊.
MLA	Jiang, Xiaobo,et al."Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part I-Modeling and Simulation Method".ieee电子器件汇刊 (2013).