A SPICE Model of Resistive Random Access Memory for Large-Scale Memory   Array Simulation

doi:10.1109/LED.2013.2293354

CORC > 北京大学 > 信息科学技术学院

	A SPICE Model of Resistive Random Access Memory for Large-Scale Memory Array Simulation
	Li, Haitong ; Huang, Peng ; Gao, Bin ; Chen, Bing ; Liu, Xiaoyan ; Kang, Jinfeng
刊名	ieee electron device letters
	2014
关键词	Circuit simulation memory array power dissipation resistive random access memory (RRAM) SPICE model COMPACT MODEL RRAM DEVICE
DOI	10.1109/LED.2013.2293354
英文摘要	A SPICE model of oxide-based resistive random access memory (RRAM) for dc and transient behaviors is developed based on the conductive filament evolution model and is implemented in large-scale array simulation. The simulations of one transistor-one resistor RRAM array up to 16 kb with wire resistance (R-wire) and capacitance (C-wire) indicate that: 1) resistance-capacitance delay during RESET and leakage current during SET have significant impact on write operations; 2) with array size enlarging, the power dissipation increases during RESET but decreases during SET; and 3) the increased Rwire and Cwire lead to the degradation of high resistance state and the fluctuation of low resistance state, respectively.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000331377500021&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; SCI(E); EI; 14; ARTICLE; kangjf@pku.edu.cn; 2; 211-213; 35
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/152180]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Li, Haitong,Huang, Peng,Gao, Bin,et al. A SPICE Model of Resistive Random Access Memory for Large-Scale Memory Array Simulation[J]. ieee electron device letters,2014.
APA	Li, Haitong,Huang, Peng,Gao, Bin,Chen, Bing,Liu, Xiaoyan,&Kang, Jinfeng.(2014).A SPICE Model of Resistive Random Access Memory for Large-Scale Memory Array Simulation.ieee electron device letters.
MLA	Li, Haitong,et al."A SPICE Model of Resistive Random Access Memory for Large-Scale Memory Array Simulation".ieee electron device letters (2014).