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	A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller
	Chen HongMing ; Ma Song ; Wang Liu ; Zhang Hao ; Pan KenYi ; Cheng YuHua
刊名	science china information sciences
	2014
关键词	all-digital delay-locked loop double-data-rate digitally controlled delay line shunt capacitor thermometer code CMOS PROCESS PLL DLL
DOI	10.1007/s11432-014-5226-1
英文摘要	A new low-power, area efficiency all-digital delay-locked loop (ADDLL) circuit is proposed for DDR3 application. The ADDLL can process the input clock frequency ranging from 333 MHz to 800 MHz (DDR3-667/800/1066/1600) by using Phase Detector (PD), Delay Control Delay Line (DCDL), Digital Loop Filter Controller (DLFC) and Delay Generator (DG). To achieve 1.6 Gb/s/pin operation, a novel DCDL scheme is employed. The DCDL has a small delay with a shunt capacitor based digitally controlled delay element. A split-control thermometer-code generator generates the control voltages used to set a current in the current-starved inverters. The testchip fabricated with a 40-nm CMOS process gives the ADDLL data rate of 667 Mbps-1.6 Gbps. Experimental results that show the power consumption is 1.87 mW at 1.1 V with active area is 0.0137 mm(2).; Computer Science, Information Systems; SCI(E); EI; 0; ARTICLE; chenhongming@pku.edu.cn; 12; 1-8; 57
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/151955]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Chen HongMing,Ma Song,Wang Liu,et al. A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller[J]. science china information sciences,2014.
APA	Chen HongMing,Ma Song,Wang Liu,Zhang Hao,Pan KenYi,&Cheng YuHua.(2014).A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller.science china information sciences.
MLA	Chen HongMing,et al."A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller".science china information sciences (2014).

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