Optimizing set performance for phase change memory with dual pulses set method | |
Wang, Yueqing1,2; Cai, Daolin1; Chen, Yifeng1; Wang, Yuchan1,2; Wei, Hongyang1,2; Huo, Ruru1,3; Chen, Xiaogang1; Song, Zhitang1 | |
刊名 | Ecs solid state letters
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2015 | |
卷号 | 4期号:7页码:Q32-q35 |
ISSN号 | 2162-8742 |
DOI | 10.1149/2.0041507ssl |
通讯作者 | Wang, yueqing(yqwang@mail.sim.ac.cn) |
英文摘要 | Applying a high power pulse (hpp) before the standard single box set pulse accelerates the crystallization process and reduces the set resistance of phase change memory (pcm) cells. the effects of hpp on set resistance distribution are characterized and analyzed. dual pulses set method (d-set) is proposed and compared with some conventional set methods. the results gathered across a 16 kbits block of a 64 mbits pcm test chip in 40 nm cmos process show that d-set achieves the fastest set speed, the narrowest set resistance distribution and smallest drift coefficient with set time of 300 ns. (c) 2015 the electrochemical society. all rights reserved. |
WOS研究方向 | Materials Science ; Physics |
WOS类目 | Materials Science, Multidisciplinary ; Physics, Applied |
语种 | 英语 |
出版者 | ELECTROCHEMICAL SOC INC |
WOS记录号 | WOS:000356879700004 |
内容类型 | 期刊论文 |
URI标识 | http://www.corc.org.cn/handle/1471x/2376388 |
专题 | 中国科学院大学 |
通讯作者 | Wang, Yueqing |
作者单位 | 1.Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, State Key Lab Funct Mat Informat & Nanotechnol La, Shanghai 200050, Peoples R China 2.Univ Chinese Acad Sci, Beijing 100080, Peoples R China 3.Shanghaitech Univ, Shanghai 200031, Peoples R China |
推荐引用方式 GB/T 7714 | Wang, Yueqing,Cai, Daolin,Chen, Yifeng,et al. Optimizing set performance for phase change memory with dual pulses set method[J]. Ecs solid state letters,2015,4(7):Q32-q35. |
APA | Wang, Yueqing.,Cai, Daolin.,Chen, Yifeng.,Wang, Yuchan.,Wei, Hongyang.,...&Song, Zhitang.(2015).Optimizing set performance for phase change memory with dual pulses set method.Ecs solid state letters,4(7),Q32-q35. |
MLA | Wang, Yueqing,et al."Optimizing set performance for phase change memory with dual pulses set method".Ecs solid state letters 4.7(2015):Q32-q35. |
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