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	Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS
	Fang,Xiangsheng; Deng,Honghui; Yan,Aibin; Ouyang,Yiming; Huang,Zhengfeng
刊名	Microelectronics Journal
	2017
卷号	Vol.61页码:43-50
关键词	SEU TOLERANT LATCH LOW-COST HIGH-PERFORMANCE TECHNOLOGY SYSTEMS
ISSN号	0026-2692
URL标识	查看原文
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/2155643
专题	安徽大学
作者单位	1.Hefei Univ Technol, Sch Comp & Informat, Hefei, PR, Peoples R China 2.Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei, PR, Peoples R China 3.Anhui Univ, Sch Comp Sci & Technol, Hefei, PR, Peoples R China
推荐引用方式 GB/T 7714	Fang,Xiangsheng,Deng,Honghui,Yan,Aibin,et al. Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS[J]. Microelectronics Journal,2017,Vol.61:43-50.
APA	Fang,Xiangsheng,Deng,Honghui,Yan,Aibin,Ouyang,Yiming,&Huang,Zhengfeng.(2017).Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS.Microelectronics Journal,Vol.61,43-50.
MLA	Fang,Xiangsheng,et al."Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS".Microelectronics Journal Vol.61(2017):43-50.

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