Yield evaluation of analog placement with arbitrary capacitor ratio (EI收录) | |
Chen, Jwu-E[1]; Luo, Pei-Wen[2]; Wey, Chin-Long[1] | |
会议名称 | Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009 |
会议日期 | March 16, 2009 - March 18, 2009 |
会议地点 | San Jose, CA, United states |
关键词 | Capacitors Circuit simulation Correlation methods Random errors Systematic errors |
URL标识 | 查看原文 |
内容类型 | 会议论文 |
URI标识 | http://www.corc.org.cn/handle/1471x/2081021 |
专题 | 华南理工大学 |
作者单位 | 1.[1] Department of Electrical Engineering National Central University Jhongli, Taoyuan, China 2.[2] SoC Technology Center Industrial Technology Research Institute Hsin Chu, Taoyuan, China |
推荐引用方式 GB/T 7714 | Chen, Jwu-E[1],Luo, Pei-Wen[2],Wey, Chin-Long[1]. Yield evaluation of analog placement with arbitrary capacitor ratio (EI收录)[C]. 见:Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009. San Jose, CA, United states. March 16, 2009 - March 18, 2009. |
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