Design of an Optimized Low-latency Interrupt Controller for IMS-DPU (CPCI-S收录) | |
Guo, Zijia[1]; Wang, Teng[1]; Wang, Xin-An[1]; Hu, Ziyi[2] | |
会议名称 | 2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) |
关键词 | low-latency interrupt controller interrupt handling software stack hardware stack tail chaining later arrivals |
URL标识 | 查看原文 |
内容类型 | 会议论文 |
URI标识 | http://www.corc.org.cn/handle/1471x/2051118 |
专题 | 华南理工大学 |
作者单位 | 1.[1]Peking Univ, Shenzhen Grad Sch, Key Lab Integrated Microsyst, Shenzhen 518055, Peoples R China 2.[2]Inst Microelect Chinese Acad Sci, Beijing, Peoples R China |
推荐引用方式 GB/T 7714 | Guo, Zijia[1],Wang, Teng[1],Wang, Xin-An[1],等. Design of an Optimized Low-latency Interrupt Controller for IMS-DPU (CPCI-S收录)[C]. 见:2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON). |
个性服务 |
查看访问统计 |
相关权益政策 |
暂无数据 |
收藏/分享 |
除非特别说明,本系统中所有内容都受版权保护,并保留所有权利。
修改评论