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	Structuring analog fractance circuit for 1/2 order fractional calculus
	Pu, Yifei; Yuan, Xiao; Liao, Ke; Zhou, Jiliu; Zhang, Ni; Zeng, Yi; Pu, Xiaoxian
刊名	ASICON 2005: 2005 6th International Conference on ASIC, Proceedings
	2005
卷号	Vol.2页码:1039-1042
URL标识	查看原文
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/1998936
专题	四川大学
作者单位	School of Electronics and Information, Sichuan University, Sichuan province 610064, China School of Law, Sichuan University, Sichuan province 610
推荐引用方式 GB/T 7714	Pu, Yifei,Yuan, Xiao,Liao, Ke,et al. Structuring analog fractance circuit for 1/2 order fractional calculus[J]. ASICON 2005: 2005 6th International Conference on ASIC, Proceedings,2005,Vol.2:1039-1042.
APA	Pu, Yifei.,Yuan, Xiao.,Liao, Ke.,Zhou, Jiliu.,Zhang, Ni.,...&Pu, Xiaoxian.(2005).Structuring analog fractance circuit for 1/2 order fractional calculus.ASICON 2005: 2005 6th International Conference on ASIC, Proceedings,Vol.2,1039-1042.
MLA	Pu, Yifei,et al."Structuring analog fractance circuit for 1/2 order fractional calculus".ASICON 2005: 2005 6th International Conference on ASIC, Proceedings Vol.2(2005):1039-1042.

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