efficient reconfiguration algorithm for three-dimensional vlsi arrays

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	efficient reconfiguration algorithm for three-dimensional vlsi arrays
	Jiang Guiyuan ; Jigang Wu ; Sun Jizhou
	2012
会议名称	2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
会议日期	May 21, 2012 - May 25, 2012
会议地点	Shanghai, China
关键词	Algorithms Distributed parameter networks Fault tolerance Heuristic algorithms Parallel architectures Reconfigurable architectures Three dimensional computer graphics
页码	261-265
中文摘要	Reconfigurable VLSI array is a well known fault tolerant architecture for parallel computing, but few reconfiguration approaches are reported so far for three-dimensional (3D) arrays due to the high complexity of reconfiguration. This paper is devoted to develop reconfiguration algorithm for three-dimensional degradable VLSI arrays. Three bypass schemes and three rerouting schemes are proposed to reconfigure a 3D host array with faults resulting in a target sub-array without faults. Moreover, a heuristic algorithm based on plane rerouting is proposed to construct a target sub-array on the selected rows and columns. It is also proved that the reconfiguration problem considered in this paper on the selected rows and columns(MPSRC) can be optimally solvable in linear time. Empirical study shows that the proposed algorithm produces target arrays with good harvest for the case of the fault rate no more than 5%, that is often occurred in real applications. © 2012 IEEE.
英文摘要	Reconfigurable VLSI array is a well known fault tolerant architecture for parallel computing, but few reconfiguration approaches are reported so far for three-dimensional (3D) arrays due to the high complexity of reconfiguration. This paper is devoted to develop reconfiguration algorithm for three-dimensional degradable VLSI arrays. Three bypass schemes and three rerouting schemes are proposed to reconfigure a 3D host array with faults resulting in a target sub-array without faults. Moreover, a heuristic algorithm based on plane rerouting is proposed to construct a target sub-array on the selected rows and columns. It is also proved that the reconfiguration problem considered in this paper on the selected rows and columns(MPSRC) can be optimally solvable in linear time. Empirical study shows that the proposed algorithm produces target arrays with good harvest for the case of the fault rate no more than 5%, that is often occurred in real applications. © 2012 IEEE.
收录类别	EI
会议主办者	IEEE Computer Society Technical Committee on Parallel Processing
会议录	Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
语种	英语
ISBN号	9780769546766
内容类型	会议论文
源URL	[http://ir.iscas.ac.cn/handle/311060/15781]
专题	软件研究所_软件所图书馆_会议论文
推荐引用方式 GB/T 7714	Jiang Guiyuan,Jigang Wu,Sun Jizhou. efficient reconfiguration algorithm for three-dimensional vlsi arrays[C]. 见:2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012. Shanghai, China. May 21, 2012 - May 25, 2012.