fast complete memory consistency verification

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	fast complete memory consistency verification
	Yunji Chen ; Yi Lv ; Weiwu Hu ; Tianshi Chen ; Haihua Shen ; Pengyu Wang ; Hong Pan
	2009
会议名称	2008 IEEE International Conference on Mechatronics and Automation, ICMA 2008
会议日期	August 5,
会议地点	Takamatsu, Japan
关键词	Computer architecture
页码	381-392
英文摘要	The verification of an execution against memory consistency is known to be NP-hard. This paper proposes a novel fast memory consistency verification method by identifying a new natural partial order: time order. In multiprocessor systems with store atomicity, a time order restriction exists between two operations whose pending periods are disjoint: the former operation in time order must be observed by the latter operation. Based on the time order restriction, memory consistency verification is localized: for any operation, both inferring related orders and checking related cycles need to take into account only a bounded number of operations. Our method has been implemented in a memory consistency verification tool for CMP (Chip Multi Processor), named LCHECK. The time complexity of the algorithm in LCHECK is O(C^pp ²n²) (where C is a constant, p is the number of processors and n is the number of operations) for soundly and completely checking, and O(p³n) for soundly but incompletely checking. LCHECK has been integrated into both pre and post silicon verification platforms of the Godson-3 microprocessor, and many bugs of memory consistency and cache coherence were found with the help of LCHECK. © 2008 IEEE.
收录类别	EI
会议录	Proceedings - International Symposium on High-Performance Computer Architecture
会议录出版地	United States
语种	英语
ISSN号	15300897
ISBN号	9781424429325
内容类型	会议论文
源URL	[http://124.16.136.157/handle/311060/8544]
专题	软件研究所_软件所图书馆_2009年期刊/会议论文
推荐引用方式 GB/T 7714	Yunji Chen,Yi Lv,Weiwu Hu,et al. fast complete memory consistency verification[C]. 见:2008 IEEE International Conference on Mechatronics and Automation, ICMA 2008. Takamatsu, Japan. August 5,.