Effects of Non-ideal Switches on Speed of SC Integrator
Xu BS(徐保树); Shi ZL(史泽林); Wang X(王霄); Zhao YH(赵耀宏)
2016
会议名称2016 13th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016
会议日期October 25-28, 2016
会议地点Hangzhou, China
关键词Switch switched capacitor(SC) integrator dynamic error(DE) optimization
页码1-3
通讯作者Wang X(王霄)
中文摘要This paper presents a method with which the switches in the classical switched capacitor(SC) integrator can be optimized to achieve smallest layout area in the meanwhile maintaining circuit speed within demand. After introduction of structure and function of the SC integrator that is composed of capacitors, switches and op amp, the reason why switches involved should be optimized is given that is due to the noneideal factors of switch. The method at first calculates the maximum on-resistance of a CMOS switch in accordance with speed specification, then the width and length of channel of the PMOS and NMOS involved in a CMOS switch are obtained through numerical simulations by HSPICE. The results show that a switch should be designed with 0.3μm/0.35μm for PMOS and NMOS, respectively, to achieve smallest layout area for the SC integrator implemented by TSMC 0.18 um Mixed Signal SALICIDE technology.
产权排序1
会议录2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Proceedings
会议录出版者IEEE
会议录出版地New York
语种英语
ISBN号978-1-4673-9719-3
内容类型会议论文
源URL[http://ir.sia.cn/handle/173321/21054]  
专题沈阳自动化研究所_光电信息技术研究室
作者单位1.Shenyang Institute of Automation, Chinese Academy of Sciences
2.Key Laboratory of Opto-Electronic Information Processing, Chinese Academy of Sciences, Shenyang 110016, China
3.University of the Chinese Academy of Sciences
推荐引用方式
GB/T 7714
Xu BS,Shi ZL,Wang X,et al. Effects of Non-ideal Switches on Speed of SC Integrator[C]. 见:2016 13th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016. Hangzhou, China. October 25-28, 2016.
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