In order to achieve real-time detection of SIFT keypoints through hardware computation on FPGA, the original algorithm was redesigned to accommodate the parallel computation and pipelined structure of hardware. The computation accuracy of fixed-point number is improved by the new scheme, while the computation amount of the whole algorithm is greatly reduced and hardware cost is saved. In the aspect of performance, the new scheme is as robust to image noise as the original algorithm, while the scale invariance of keypoints has been improved dramatically.