QQ客服 官方微博 反馈留言

题名	面向VLIW结构的DSP编译器的设计与实现
作者	王敏
学位类别	博士
答辩日期	2009-05-27
授予单位	中国科学院声学研究所
授予地点	声学研究所
关键词	VLIW 编译器 移植 SIMD 功耗模型
其他题名	Design and Implementation of a VLIW DSP Compiler
学位专业	信号与信息处理
中文摘要	超长指令字（VLIW）结构是现代高端数字信号处理器DSP 普遍使用的结构。VLIW 采用指令静态调度，指令并行性挖掘、相关性检查、指令调度等职能均由编译器实现。因此开发高性能的VLIW 编译器，对挖掘处理器的性能有重要的意义。另一方面，DSP 为了适应多媒体处理的大数据量、高并行性等特点，以及嵌入式应用的低功耗要求，将VLIW 结构与单指令流多数据流SIMD 技术、低功耗设计相结合，这些新的结构特性对编译器的设计和优化提出了新的需求与挑战。 本文的研究重点是设计和实现一款面向VLIW 结构的DSP 编译器，并探讨编译器对SIMD 的支持以及低功耗编译技术。 利用可重定向编译器IMPACT 的前端和其代码生成器模板，本文设计和实现了面向VLIW DSP 芯片SuperV2 的编译器。编译器代码生成器的设计结合了SuperV2的结构特点和IMPACT 提供的支持，实现了指令注释、指令调度、寄存器分配以及汇编代码生成。指令注释解决了推断比较指令注释、除法注释等机器相关的问题。指令调度采用寄存器压力敏感的列表调度。寄存器分配采用基于图着色的分簇寄存器分配方法。汇编代码根据SuperV2 汇编器的格式要求进行生成。 SIMD 技术能有效的提高数据并行性，是媒体处理领域的一项重要技术。本文研究了利用内在函数支SIMD 的方法，实现了SIMD 指令的识别和生成。为简化编译器前端对SIMD128 位数据的支持，本文提出伪数据类型的方法。 随着芯片集成度的不断提高，软硬件协同的低功耗设计已经变得越来越重要。本文分析了低功耗编译的模型和方法，并针对SuperV2 指令包的特点，设计了SuperV2基于指令包的编译功耗模型。 实验表明，编译DSP 核心程序时，对比基于GCC 版本的编译器，新的编译器生成的指令数下降30%，并行包数下降8%。进一步实验表明，在降低RAW 延迟后，均值IPC 从1.5 升至1.7。运行更大的程序时，均值IPC 分布为1.6 到3 之间。
英文摘要	Very Long Instruction Word (VLIW) architecture is widely used in today’s high-end Digital Signal Processors (DSP). VLIW adopts static scheduling and requires the compiler to do ILP exploiting, instruction scheduling and dependence checking. As a result of that, VLIW relies heavily on the performance of the compiler. To develop a high performance compiler has great significance on the final quality of VLIW processors. On the other hand, DSP combines the Single Instruction Multiple Data (SIMD) and low power designs with the VLIW architecture, so it could speed up the processing of large amounts of parallel data in multimedia applications, and satisfy the power requirements of embedded applications. These new extensions and designs propose new challenges to the design and optimization of compilers. This dissertation presents the design and implementation of a VLIW DSP compiler. SIMD support and low power compilation technology are also discussed. Based on the front-end and code generator template of a retargetable compiler IMPACT, a compiler for VLIW DSP chip SuperV2 is constructed. The code generator fully supports the architecture and characteristics of SuperV2. It implements the processor dependent instruction annotation, instruction scheduling, register allocation and assembly code generation. In the annotation part, machine specific problems like annotating predicate-compare instructions are solved. In the scheduling part, a register-pressure-sensitive list scheduling algorithm is adopted. In the register allocation part, a clustered-register allocation algorithm based on color graphing is used. Lastly, assembly code with the format of SuperV2 assembler is generated. SIMD is an important technology in the multimedia processing field. An intrinsic function mechanism is implemented in the compiler to recognize and generate SIMD instructions. A pseudo data type is proposed to represent the 128-bit data, with the purpose of the simplifying the compiler’s front-end. With the increase of chip integration, low power design has become more important. Low power optimization should beimplemented in both hardware and software. In this paper, low power compiling models and techniques are analyzed, and an instruction package level power model is proposed for SuperV2. Experimental results show that, compared with our former GCC version compiler, the new compiler has a 30% decrease of instruction number and an 8% decrease of parallel package number on core DSP programs. The average IPC has increased from 1.5 to 1.7 after reducing the RAW latency. The distribution of average IPC is from 1.6 to 3 when testing larger programs.
语种	中文
公开日期	2011-05-07
页码	84
内容类型	学位论文
源URL	[http://159.226.59.140/handle/311008/564]
专题	声学研究所_声学所博硕士学位论文_1981-2009博硕士学位论文
推荐引用方式 GB/T 7714	王敏. 面向VLIW结构的DSP编译器的设计与实现[D]. 声学研究所. 中国科学院声学研究所. 2009.

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。