| 题名 | 超低功耗流水线A/D转换器设计 |
| 作者 | 范兵 |
| 学位类别 | 博士 |
| 答辩日期 | 2009-05-27 |
| 授予单位 | 中国科学院声学研究所 |
| 授予地点 | 声学研究所 |
| 关键词 | 模数转换器 低功耗 流水线 并行结构 开关栅增压电路 |
| 其他题名 | The Design of Very Low Power Pipeline A/D Converter |
| 学位专业 | 信号与信息处理 |
| 中文摘要 | 高速、中等精度的模数转换器（ADCs）被广泛的应用在数字通信、视频处理等系统中。随着无线应用和便携设备迅速发展，单芯片集成的片上系统的已成为发展趋势。功耗成为必须关注的首要问题，可系统集成的高速、低功耗ADC成为模拟集成电路设计领域的研究热点。流水线ADC被证明是实现高速、中等精度ADC效率最高的结构。 本文对流水线ADC设计实现中的各种非理想特性进行了深入的研究，对各组成模块的误差进行了定量分析。研究了流水线ADC各级分辨率的选取与整个系统的功耗的关系，对与速度相关寄生电容的影响进行了建模，并提出了流水线ADC系统功耗优化算法。此算法可自动化完成给定的约束条件下流水线ADC系统功耗最优化设计。 对流水线ADC的系统结构进行改进，采用双路ADC并行工作，即由两路25MS/s的ADC以时间交织的方式工作，实现采样速率50MS/s的ADC。在两路ADC的级电路之间实现运放共享复用降低系统的功耗。与传统的相邻流水线级电路之间的运放共享复用技术相比，应用此方法可以实现流水线级电路的按比例缩减，提高功耗效率。 为了降低系统的功耗，对具体电路设计进行了一系列改进和优化：采用SHA-Less结构；依照功耗优化算法的结果，选择最优的单级分辨率及电容逐级递减，从而降低了功耗；优化运放设计，采用共栅频率补偿和分离补偿电容的技术。有效的提高运放的单位增益带宽，改善相位裕度，降低运放的功耗；提出了一种改进的开关栅增压电路，有效的降低了沟道电荷注入和时钟馈通引入的非线性失真。 本研究采用0.18μm CMOS工艺，设计了10-bit，采样速率为50 MS/s的低功耗ADC，功耗仅为9mW，功耗优质因子FOM为0.76pJ/step，达到国际先进水平。说明此研究可在保证ADC性能的前提下，达到功耗优化的目的。 |
| 英文摘要 | High speed, medium-resolution, analog-to-digital converters (ADCs) are widely used in many electronic applications, such as digital communication systems, video signal processing systems. With the rapid development of wireless and portable application, power dissipation becomes a primary concern. The research of low-power，high-speed ADC for the SOC application has become an important topic in the filed of analog IC. Pipeline architecture has proven to be the most efficient architectures to deliver these high-speed, medium-resolution ADCs. To make sure the system level design can be implemented in real circuits, the non-idealities of the circuit realization are carefully investigated. The resolution per stage plays an important role in determining overall power dissipation of a pipeline ADC. A power optimization algorithm was developed and the effect of parasitic capacitors related to speed was considered. The whole ADC consists of two 25 Ms/s ADCs working time-interleaved to achieve a 50Ms/s sample rate. An amplifier sharing technique between two channels was proposed. In this amplifier sharing technique, it is possible to optimize an amplifier for each conversion stage compared to the conventional amplifier sharing technique. In order to reduce the power consumption, a series of techniques was adopted in the circuit design: SHA-less architecture; resolution distribution, capacitor scaling, current control of each stage according to the power optimization algorithm result; improving the op-amp performance by using cascoded Miller compensation and compensation capacitor splitting technique; proposed a novel bootstrapped switch which reduce the effect of charge injection and clock feedthrough effectively. According to the analysis, a 10-bit, 50Ms/s ADC is implemented in 0.18μm CMOS process. The power consumption is only 9mW, with the state-of-the-art FOM which is 0.76pJ/step. |
| 语种 | 中文 |
| 公开日期 | 2011-05-07 |
| 页码 | 127 |
| 内容类型 | 学位论文 |
| 源URL | [http://159.226.59.140/handle/311008/490]  |
| 专题 | 声学研究所_声学所博硕士学位论文_1981-2009博硕士学位论文 |
| 推荐引用方式 GB/T 7714 | 范兵. 超低功耗流水线A/D转换器设计[D]. 声学研究所. 中国科学院声学研究所. 2009. |
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